1. Field of the Invention
The present invention relates to a semiconductor memory, which has insulating layers and charge storage layers that improve erasure characteristics of a memory cell having insulating layers and charge storage layers, while achieving even higher integration.
2. Description of the Related Art
A nonvolatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) or the like has been developed. With such kind of memory, charges injected from a channel into a charge storage electrode via an insulating layer, due to tunneling current, are stored as digital information. The change in a metal-oxide semiconductor memory cell transistor (MOSFET) conductance that corresponds to the quantity of that charge is measured, and information is read out. Particularly, there has been extensive research due to the fact that metal-oxide-nitride-oxide-semiconductor (MONOS) memory is a memory that uses a nitride (SiN) film as a charge storage layer. Such a charge storage layer is used where there is a possibility that the programming operation or the erasure operation can be implemented at a lower voltage than, for example, memory using a floating gate made from polysilicon.
In this case, MONOS memory, for example, as described in U.S. Pat. Nos. 6,137,718 and 6,040,995 has a structure stacked in the order of a semiconductor substrate, a silicon oxide film (first silicon oxide film) through which charges are intended to pass, a silicon nitride film (charge storage layer), a silicon oxide film (second silicon oxide film), which blocks currents from flowing between the silicon nitride film and a polysilicon region, and the polysilicon region.
However, with conventional MONOS memory, since the difference in the second silicon oxide film thickness and the first silicon oxide film thickness is small, the electrons of the control electrode are injected into the charge storage layer upon erasure that utilizes injection of holes from the semiconductor substrate into the charge storage layer. Accordingly, since a large erasure voltage increases the quantity of the injected electrons in the control electrode to be almost equivalent to the quantity of the injected holes, there was a problem where the erasure threshold voltage would not become lower than a specific value, that is, would not sufficiently decrease. Therefore, there was a difficult problem of sufficiently securing isolation of the programming threshold voltage and the erasure threshold voltage.
In addition, in the case of injecting holes using the current passing through the first silicon oxide film as the tunneling current, there was a problem where, due to an increase in the quantity of the injected electrons that pass through the second silicon oxide film, the increase in the quantity of the positive charges in the charge storage layer was reduced, resulting in a longer erasure time.
Furthermore, Japanese Laid-Open Patent Application No. Hei 5-82795 and U.S. Pat. No. 5,286,994 provide a structure in which the charge storage layer is assumed to be a multi-layered stacked layer, where the film thickness becomes thicker as the charge storage layer is farther from the first gate insulating layer. Specific conditions for the structure and film thickness of the film that blocks currents from flowing between the silicon nitride film and the polysilicon region, and the problem that electrons of the control electrode are injected into the charge storage layer upon erasure are not disclosed in the above-described patent documents. Moreover, Japanese Laid-Open Patent Application No. Hei 11-40682 discloses an example where the second insulating layer is a stacked layer configured with a silicon nitride film subjected to thermal oxidation, and a deposited silicon oxide film. The application also does not disclose specific conditions for the structure and film thickness regarding how to form the stacked layer relative to the problem that electrons of the control electrode are injected into the charge storage layer upon erasure.
The experimental fact that the inventers discovered a charge centroid position in the erase saturation state using a band structural diagram of the MONOS structure has already been disclosed in Japanese Laid-open Patent Application No. 2003-078043.
In addition, the fact that doping boron to an insulating layer including SiO permits the insulating layer function as an acceptor (electron trap), having negative charges is reported in G. Pacchioni and M. Vezzoli, “Electronic structure of the paramagnetic boron oxygen hole center in B-doped SiO2”, Physical Review B, Vol. 64, pp. 155201-155207, for example.
As described above, with the conventional MONOS memory cell structure, if the erasure voltage was increased to carry out high-speed erasure operations, there was the problem of insufficient reduction in the erasure threshold voltage. Furthermore, there was a problem where due to an increase in the quantity of the injected electrons that pass through the second silicon oxide film, the quantity of positive charge in the charge storage layer was reduced, resulting in a longer erasure time.